This invention relates to the manufacture of semiconductor devices, and particularly to the use of novel lead frame assemblies in such manufacture and to the resulting devices.
The use of lead frames in the manufacture of semiconductor devices is known. Such lead frames generally comprise a flat sheet of metal which is partially etched away to leave a pattern of narrow leads which converge towards a central area of the pattern. Commonly, one of the leads extends beyond the others and expands, within the lead frame central area, into a chip mounting pad.
In use, a semiconductor chip is mounted on the mounting pad. The upper surface of the chip contains a number of peripherally spaced bonding pads each connected, via runners on the chip, to various circuit components contained within the chip. Bonding wires are bonded between the lead ends and respective ones of the chip bonding pads. Thereafter, the chip, the bonding wires and the inner ends of the leads are all encapsulated in a plastic enclosure. Then, surrounding portions of the lead frame external to the enclosure are cutaway leaving a plurality of terminal leads extending outwardly from the enclosure.
Examples of various lead frame arrangements and manufacturing processes using them are disclosed in the following U.S. patents, the subject matter of which are incorporated herein by reference: U.S. Pat. Nos. 4,714,952 (Takekawa et al); 4,829,403 (Harding); 4,839,713 (Teraoka et al); 3,629,668 (Hingorany); 4,751,611 (Arai); 5,049,977 (Sako) and 5,223,739 (Katsumata).
The present invention provides a variation over known lead frame assemblies and provides certain manufacturing advantages. Additionally, the present invention facilitates the incorporation of two or more chips within a single enclosure.